Method and device for recombining runtime instruction

ABSTRACT

A method for recombining runtime instruction comprising: an instruction running environment is buffered; the machine instruction segment to be scheduled is obtained; the second jump instruction which directs an entry address of an instruction recombining platform is inserted before the last instruction of the obtained machine instruction segment to generate the recombined instruction segment comprising the address A″; the value A of the address register of the buffered instruction running environment is modified to the address A″; the instruction running environment is recovered. A device for recombining the runtime instruction comprising: an instruction running environment buffering and recovering unit suitable for buffering and recovering the instruction running environment; an instruction obtaining unit suitable for obtaining the machine instruction segment to be scheduled; an instruction recombining unit suitable for generating the recombined instruction segment comprised the address A″; and an instruction replacing unit suitable for modifying the value of the address register of the buffered instruction running environment to the address of the recombined instruction segment. The monitoring and control of the runtime instruction of the computing device is completed.

CROSS REFERENCE TO RELATED APPLICATIONS

This application is a continuation application of U.S. patentapplication Ser. No. 14/113,570, entitled “Method and Device forRecombining Runtime Instruction”, filed on Oct. 23, 2013, which is aSection 371 National Stage Application of International Application No.PCT/CN2011/073495, filed on Apr. 29, 2011, each of which is incorporatedherein by reference in its entirety.

FIELD OF THE DISCLOSURE

The present disclosure is related to instruction processing in acomputing device, and more particularly, to a runtime instructionrecombination method and device.

BACKGROUND OF THE DISCLOSURE

The running of a computer is a process that software directs andcontrols hardware to generate results. However, during the running of acomputer, because of program bugs, system backdoors, systemvulnerability, malicious codes, .etc., users may get partially ortotally unexpected results.

To solve this problem, there are provided many methods nowadays, such asstatic code analysis, vulnerability detection, setting up a maliciouscode list (i.e., anti-virus software). However, the static code analysiscan only determine the correctness of logics and parameter definitions,which is syntax analysis; vulnerability detection is to try a variety oflogic assumptions to find logical vulnerability, which is also based onstatic analysis; and setting up a malicious code list can only solvelimited problems as is well-known.

The above methods cannot fully solve existing problems, for they do notanalyze runtime instructions.

Therefore, there is a need for a method which can monitor runtimeinstructions in a computing device.

SUMMARY

Embodiments of the present disclosure provide a runtime instructionrecombination method and device, so as to monitor and control runtimeinstructions in a computing device.

According to one aspect of the present disclosure, there is provided aruntime instruction recombination method, including:

storing an instruction execution context;

acquiring a machine instruction segment to be scheduled; inserting asecond control transfer instruction before the last instruction of theacquired machine instruction segment to be scheduled, the second controltransfer instruction pointing to an entry address of an instructionrecombination platform, which generates a recombined instruction segmentwith address A″; modifying value A of an address register in the storedinstruction execution context to the address A″ of the recombinedinstruction segment; and

restoring the instruction execution context, wherein the addressregister's value is updated.

Optionally, acquiring a machine instruction segment to be scheduledincludes: reading an address of a machine instruction to be scheduledfrom a CPU address register; and reading a machine instruction segmentaccording to the address of a machine instruction to be scheduled, thelast instruction of the machine instruction segment being a controltransfer instruction.

Optionally, reading a machine instruction segment according to theaddress of a machine instruction to be scheduled includes: searchingmachine instructions corresponding to the address of the machineinstruction to be scheduled, until a first control transfer instructionis found; wherein the control transfer instruction includes JMPinstruction and CALL instruction.

Optionally, after storing an instruction execution context and beforeacquiring a machine instruction segment to be scheduled, the methodfurther includes:

searching an address corresponding table according to the value A of theaddress register; the address corresponding table being used to showwhether or not the machine instruction segment to be recombined has astored recombined instruction segment with address A′;

if a record in the address corresponding table is found, modifying thevalue A of the address register to the value A′ of the record, andrestoring the instruction execution context. The address register'svalue is updated.

Optionally, the runtime instruction recombination method furtherincludes: creating a record in the address corresponding table with theaddress A″ of the recombined instruction segment and the value A of theaddress register.

Optionally, before inserting a second control transfer instruction, themethod further includes: analyzing the machine instruction segment byusing an instruction set to identify the machine instruction segment, inorder to acquire a target machine instruction to be processed; andmodifying the target machine instruction in a preset way. Theinstruction set can be X86 instruction set, MIPS instruction set, ARMinstruction set, etc.

Optionally, the target machine instruction is a store or readinstruction; and modifying the target machine instruction in a presetway includes: modifying a store or read address of the store or readinstruction to a corresponding address on a safety device.

Optionally, the target machine instruction is an I/O instruction; andmodifying the target machine instruction in a preset way includes:blocking all input instructions in the I/O instruction.

Optionally, the target machine instruction is a network transmissioninstruction; and modifying the target machine instruction in a presetway includes: determining if a destination address of the networktransmission instruction which corresponds to a remote computing deviceis a permitted address; and blocking the network transmissioninstruction if the destination address is not a permitted address.

According to another aspect of the present disclosure, there is provideda runtime instruction recombination method, including:

storing an instruction execution context;

acquiring a machine instruction segment to be scheduled;

disassembling the machine instruction segment into an assemblyinstruction segment;

inserting a second control transfer instruction before the lastinstruction of the assembly instruction segment, which generates arecombined assembly instruction segment with address A″, the secondcontrol transfer instruction pointing to an entry address of aninstruction recombination platform;

assembling the recombined assembly instruction segment to get arecombined machine instruction segment; modifying value of an addressregister in the stored instruction execution context to the address ofthe recombined assembly instruction segment; and

restoring the instruction execution context, wherein the addressregister has been updated.

Further, according to still another aspect of the present disclosure,there is provided a non-transitory computer readable medium, storing acomputer program for causing a computer to execute instructionsaccording to one of above methods.

Further, according to still another aspect of the present disclosure,there is provided a runtime instruction recombination device, including:an instruction execution context store and restore unit, being adaptedto store and restore an instruction execution context; an instructionacquiring unit, being adapted to acquire a machine instruction segmentto be scheduled after the instruction execution context store andrestore unit stores the instruction execution context; an instructionrecombination unit, being adapted to analyze and modify the machineinstruction segment to be scheduled, to generate a recombinedinstruction segment with address A″; and an instruction replacing unit,being adapted to modify value of an address register in the storedinstruction execution context to the address of the recombinedinstruction segment.

Optionally, the instruction acquiring unit is adapted to read an addressof a machine instruction to be scheduled from a CPU address register,and to read the machine instruction segment according to the address ofthe machine instruction, the last instruction of the machine instructionsegment being a control transfer instruction.

Optionally, the runtime instruction recombination device furtherincludes: an instruction searching unit, being adapted to search anaddress corresponding table with the value A of the address register inthe stored instruction execution context; the address correspondingtable being used to show whether or not the machine instruction segmentto be recombined has a stored recombined instruction segment which hasaddress A′; if a record in the address corresponding table is found, theinstruction searching unit being adapted to call the instructionreplacing unit to modify the value A of the address register to thevalue A′ of the record; if no record in the address corresponding tableis found, the instruction searching unit being adapted to create arecord in the address corresponding table using the address A″ of therecombined instruction segment and the value A of the address register.

Optionally, the instruction recombination unit includes: an instructionanalysis unit, being adapted to identify the machine instruction segmentby using an instruction set and to acquire a target machine instructionthat is to be processed; and an instruction modification unit, beingadapted to modify the target machine instruction in a preset way. Theinstruction set includes X86 instruction set, MIPS instruction set andARM instruction set.

Optionally, if the target machine instruction is a store or readinstruction, the instruction modification unit is adapted to modify astore or read address of the store or read instruction to acorresponding address on a safety device.

Optionally, if the target machine instruction is an I/O instruction, theinstruction modification unit is adapted to block all input instructionsin the I/O instruction.

Optionally, if the target machine instruction is a network transmissioninstruction, the instruction modification unit is adapted to determineif a destination address of the network transmission instruction whichcorresponds to a remote computing device is a permitted address; and ifthe destination address is not a permitted address, the instructionmodification unit is adapted to block the network transmissioninstruction.

Optionally, the instruction recombination unit further includes: adisassembling unit, being adapted to disassemble the machine instructionsegment to be scheduled before analyzing and modifying the machineinstruction segment, which generates an assembly instruction segment tobe scheduled; and an assembling unit, being adapted to assemble therecombined assembly instruction segment after analyzing and modifyingthe instruction segment, which generates recombined machine instructionsegment.

Compared with the conventional art, the methods and devices provided inembodiments of the present disclosure have the following advantages:

Instructions of a computing device may be monitored at runtime with theruntime instruction recombination method;

Instruction recombination efficiency may be improved and computingresource (e.g., CPU) of a computing device may be saved by using addresscorresponding table;

As for store and read instructions, data dump may be achieved bymodifying the destination and source address in store and readinstructions, which saves data onto a safety device to guarantee datasecurity;

As for I/O instructions, all input instructions of the I/O instructioncan be blocked, which prevents the local hardware from write operation;and all input instructions except store instruction can be blocked,which may improve the data security in a computing device;

As for network transmission instructions, data safety transmission isachieved by determining if a destination address of the networktransmission instruction which corresponds to a remote computing deviceis a permitted address and blocking the network transmission instructionif the destination address is not.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a flowchart of a runtime instruction recombination methodprovided in a first embodiment of the present disclosure;

FIG. 2 is a schematic view showing an instruction recombination processand a recombined instruction segment in the first embodiment of thepresent disclosure;

FIG. 3 is a flowchart of a runtime instruction recombination methodprovided in a second embodiment of the present disclosure;

FIG. 4 is a flowchart of a runtime instruction recombination methodprovided in a third embodiment of the present disclosure;

FIG. 5 is a schematic view showing a runtime instruction recombinationdevice provided in a seventh embodiment of the present disclosure;

FIG. 6 is a schematic view showing a runtime instruction recombinationdevice provided in an eighth embodiment of the present disclosure;

FIG. 7 is a schematic view showing an instruction recombination unit ofa runtime instruction recombination device provided in a ninthembodiment of the present disclosure;

FIG. 8 is a schematic view showing an architect or layers of a computerterminal system provided in a tenth embodiment of the presentdisclosure;

FIG. 9 is a flowchart of a whole process for data dumping provided inthe tenth embodiment of the present disclosure;

FIG. 10 is a flowchart of an initialization process S1000 in FIG. 10;

FIG. 11 is a schematic view showing a bitmap provided in the tenthembodiment of the present disclosure;

FIG. 12 is a flowchart of a data safety storage method provided in thetenth embodiment of the present disclosure;

FIG. 13 is a flowchart of a data safety reading method provided in thetenth embodiment of the present disclosure;

FIG. 14 is a flowchart of a data safety transmission method provided inthe eleventh embodiment of the present disclosure;

FIG. 15 is a schematic view showing a network structure provided in theeleventh embodiment of the present disclosure;

FIG. 16 is a schematic view showing a data safety storage deviceprovided in a twelfth embodiment of the present disclosure; and

FIG. 17 is a schematic view showing a data safety reading deviceprovided in a thirteenth embodiment of the present disclosure.

DETAILED DESCRIPTION OF THE DISCLOSURE

In order to make those skilled in the art better understand the spiritof the disclosure, embodiments according to the disclosure will beillustrated in detail hereinafter in conjunction with drawings.

The following embodiments are only specific embodiments of thedisclosure which are used to make those skilled in the art betterunderstand the spirit of the disclosure, however, the scope ofprotection of the disclosure should not be limited to the specificdescriptions of the specific embodiments, various modifications can bemade to the specific embodiments of the disclosure by those skilled inthe art without departing from the scope of spirit of the disclosure.

When a computer is running, a CPU address register keeps the address ofa next machine instruction that is to be executed. To realize monitoringof runtime machine instructions, in some embodiments of the presentdisclosure, data of this register is acquired, one or more machineinstructions to be executed are read according to the data of theregister, and the instruction segment to be scheduled which is composedof the one or more machine instructions is modified, thus the controlright may be acquired before each machine instruction is executed andanalysis of the following instructions may be performed continuously.Further, in some embodiments of the present disclosure, after the stepof acquiring the machine instruction segment to be scheduled, steps ofprocessing target instructions in the machine instruction segment to bescheduled are performed, therefore, not only are the runtimeinstructions recombined and monitored, but also target instructions aremodified and updated.

According to a first embodiment of the present disclosure, there isprovided a runtime instruction recombination method. As illustrated inFIG. 1, the method includes:

S101, storing an instruction execution context;

S102, acquiring a machine instruction segment that is to be scheduled;inserting a second control transfer instruction before the lastinstruction of the acquired machine instruction segment, the secondcontrol transfer instruction pointing at an entry address of aninstruction recombination platform, which generates a recombinedinstruction segment with address A″; and modifying the value of anaddress register of the stored instruction execution context which is Ato A″; and

S103, restoring the instruction execution context.

Specifically, before the step S101 is performed, the method furtherincludes a step to acquire the control right to run on CPU. When CPUperforms this method, the method firstly stores the instructionexecution context (i.e. step S101), that is to say, it stores the resultof the monitored instruction which has just been executed. The CPU usedin this embodiment is a central processing unit of X86-architecture; itmay also be MIPS processor or processor of ARM architecture in otherembodiments of the present disclosure. And one of ordinary skill in theart can appreciate that the CPU can be an instruction processing unit incomputing devices of any other type.

In step S101, the step of storing the instruction execution contextincludes:

pushing register data that is related to instruction execution onto astack, which includes data of registers such as the CPU addressregister. In other embodiments of the present disclosure, theinstruction execution context can also be stored at other default orspecified places or with other default or specified data structures.

In step S102, acquiring the machine instruction segment that is to bescheduled includes:

S1021, reading an address of the machine instruction to be scheduledfrom a CPU address register;

S1022, by using a control transfer instruction as the search target,searching machine instructions corresponding to the address of themachine instruction, until the first control transfer instruction isfound, the control transfer instruction including JMP instruction andCALL instruction;

S1023, defining the first control transfer instruction and machineinstructions before the first control transfer instruction as a machineinstruction segment to be scheduled; and storing the machine instructionsegment in the instruction recombination platform or other storagelocations that the instruction recombination platform is able to access.

In other embodiments of the present disclosure, acquiring the machineinstruction segment that is to be scheduled can also use non-controltransfer instructions such as write instruction or read instruction assearch target, to divide machine instructions into machine instructionsegments. And since it needs to guarantee that the instructionrecombination platform gets the control right of the CPU (i.e. thecontrol right to run on CPU) after a control transfer instruction in amachine instruction segment is executed, control transfer instructionsneed to be used as a supplemental or secondary search target, therebyresulting in machine instruction segments in smaller size.

Still in step S102, before inserting a second control transferinstruction JP2, the method provided in this embodiment can furtherinclude:

S1025, analyzing the machine instruction segment by using an instructionset to identify the machine instruction segment, in order to acquire atarget machine instruction to be processed; the instruction set can beX86, MIPS, or ARM instruction set;

S1026, modifying the target machine instruction in a preset way.

With the above steps, runtime instruction monitoring can be realized,and other processes can be performed as well, which will be furtherdiscussed in the following embodiment.

Since the purpose of this embodiment is to realize the runtimeinstruction recombination, steps S1025 and S1026 are not performed, andthe following steps are directly performed as follows: inserting asecond control transfer instruction JP2 before the last instruction(which is a control transfer instruction JP1) of the acquired machineinstruction segment, the second control transfer instruction JP2pointing at the entry address of the instruction recombination platform,which generates a recombined instruction segment with address A″;modifying the value A of the address register (i.e. the CPU addressregister) of the stored instruction execution context to A″. Theinstruction recombination platform is the execution platform of theinstruction recombination method provided in this embodiment.

Inserting JP2 is to rerun the instruction recombination platform beforeJP1 when the CPU executes the machine instruction segment that is to bescheduled; then, the instruction recombination platform continues toanalyze the next machine instruction segment to be scheduled, andrepeats the steps in the above method to finish the recombination forall instructions. More details are to be discussed in the followinganalysis of step S103.

In step S103, restoring the instruction execution context includes:popping the register data related with the instruction execution fromthe stack, wherein the destination address of the control transferinstruction which is stored in the address register has already beenmodified to A″ which is the entry address of the new machine instructionsegment. After restoring the instruction execution context, theinstruction recombination platform finishes operation this time; the CPUcontinues to perform the last instruction (which is a control transferinstruction) of the previous machine instruction segment, whichdestination address has been modified to A″ as discussed above; the CPUperforms the new machine instruction segment with the entry address ofA″. When the instruction segment with entry address of A″ is performedto the penultimate instruction (which is the second control transferinstruction JP2), the instruction recombination platform gets thecontrol right to run on the CPU again, and the instruction recombinationplatform repeats the process from step S101 to step S103.

Referring to FIG. 2, the instruction recombination process and thegeneration of a recombined instruction segment will be discussed indetail. A machine instruction set 401 that is to be scheduled is shownin FIG. 2, wherein the first control transfer instruction is a firstcontrol transfer instruction 4012; before the instructions prior to theinstruction 4012 is executed, destination address of the instruction4012 is unknown if it is an variable, therefore, it assumes that thefirst control transfer instruction 4012 points to a machine instruction4013; machine instructions including the first control transferinstruction 4012 and instructions prior to the instruction 4012constitute a machine instruction segment 4011.

Still referring to FIG. 2, when an instruction recombination platform411 runs, first the instruction execution context is stored; then themachine instruction segment 4011 is acquired; the instructionrecombination platform inserts a second control transfer instruction4113 before the first control transfer instruction 4012, the secondcontrol transfer instruction 4113 pointing to the instructionrecombination platform 411 itself, which generates a recombinedinstruction segment 4111 having an address of A″; then the value A ofthe address register in the stored instruction execution context ismodified to A″; at last, the instruction execution context is restored.

After the instruction recombination platform 411 finishes running, CPUcontinues to execute the last control transfer instruction of theprevious recombined instruction segment, which has an address register'svalue of A″. After the recombined instruction segment with an address ofA″ starts, when the second control transfer instruction 4113 is running,the instruction recombination platform 411 acquires the control right ofthe CPU again, and then continues to analyze the machine instructions tobe scheduled, thus the method of runtime instruction recombination isfinished.

Further, machine instructions of an executed program have highrepeatability; to improve instruction recombination efficiency and savecomputing resource (e.g., CPU) of the computing device, according to asecond embodiment of the present disclosure, there is provided a runtimeinstruction recombination method as shown in FIG. 3. The runtimeinstruction recombination method includes:

S201, storing the instruction execution context;

S202, searching an address corresponding table with the value A of theaddress register in the stored instruction execution context; theaddress corresponding table is used to show if the machine instructionsegment corresponding to the address A which is to be recombined has astored recombined instruction segment with an address of A′;

S203, if a record is found, modifying value A of the address register tovalue A′ of the record, and restoring the instruction execution context;the method is finished this time;

S204, if no record is found, acquiring a machine instruction segment tobe scheduled; inserting a second control transfer instruction before thelast instruction of the acquired machine instruction segment, the secondcontrol transfer instruction pointing to the entry address of theinstruction recombination platform, which generates a recombinedinstruction segment with an address of A″; and modifying the value A ofaddress register in the stored instruction execution context to addressA″;

S205, restoring the instruction execution context.

Also, the step S204 may further include: creating a record in theaddress corresponding table using the address A″ and address A. And therecombined instruction segment with address A″ is stored in theinstruction recombination platform for reuse.

By using the address corresponding table, the method saves the computingresources and improves efficiency of runtime instruction recombination.

In the above embodiments, machine instructions, i.e. binary machinecodes, are directly manipulated or handled; in other embodiments of thepresent disclosure, since there may be further operations likeinstruction modifications, the machine instruction segment to bescheduled can be firstly disassembled into assembly code segment forlater use, and the assembly code segment is to be assembled into binarymachine code before restoring the instruction execution context.

According to a third embodiment of the present disclosure, there isprovided a runtime instruction recombination method, including:

S301, storing a current instruction execution context;

S302, searching an address corresponding table with a value A of anaddress register in the stored instruction execution context;

S303, if a corresponding record is found, modifying value A of theaddress register to value A′ of the record, and restoring theinstruction execution context;

S304, if no record is found, a generating method of recombinedinstruction is shown in FIG. 4, including:

S3041, acquiring a machine instruction segment to be scheduled;

S3042, disassembling the machine instruction segment into an assemblyinstruction segment;

S3043, analyzing the assembly instruction segment by using aninstruction set to identify the assembly instruction segment, so as toacquire a target assembly instruction to be processed;

S3044, inserting a second control transfer instruction JP2 before thelast instruction of the assembly instruction segment, the second controltransfer instruction JP2 pointing to an entry address of the instructionrecombination platform, which generates a recombined instruction segmentwith an address of A″;

S3045, assembling the modified assembly instruction segment to get arecombined machine instruction segment;

S3046, creating a record in the address corresponding table with theaddress A″ and address A;

S3047, modifying the value A of address register in the storedinstruction execution context to the address A″;

S305, restoring the instruction execution context.

Step S3042 and S3045 are corresponding disassembling and assemblingsteps. It's easy to perform further analyzing and modifying steps afterthe machine instruction segment is disassembled into assemblyinstruction segment. Other steps are similar with those in the aboveembodiment, which will not be discussed again.

The above runtime instruction recombination method provides basis forfurther applications. The following embodiments provide various runtimeinstruction recombination methods which perform different processing onmachine instructions including store/read instruction, I/O instructionand network transmission instruction.

For a store/read instruction, according to a fourth embodiment of thepresent disclosure, there is provided a runtime instructionrecombination method, including:

S401, storing a current instruction execution context;

S402, searching an address corresponding table with value A of anaddress register in the stored instruction execution context;

S403, if a corresponding record is found, modifying the value A of theaddress register to value A′ of the record, and restoring theinstruction execution context;

S404, if no record is found, a generating method of a recombinedinstruction includes:

S4041, acquiring a machine instruction segment to be scheduled;

S4042, disassembling the machine instruction segment into an assemblyinstruction segment;

S4043, analyzing the assembly instruction segment by using aninstruction set to identify the assembly instruction segment, so as toacquire a target assembly instruction to be processed; the targetassembly instruction being a store/read instruction;

S4044, if the assembly instruction segment includes a store/readinstruction, modifying a store or read address of the store/readinstruction to corresponding addresses on a safety device;

S4045, inserting a second control transfer instruction JP2 before thelast instruction of the assembly instruction segment, the second controltransfer instruction JP2 pointing to an entry address of the instructionrecombination platform, which generates a recombined instruction segmentwith an address of A″;

S4046, assembling the modified assembly instruction segment to get arecombined machine instruction segment;

S4047, creating a record in the address corresponding table with theaddress A″ and address A;

S4048, modifying the value A of the address register in the storedinstruction execution context to the address A″;

S405, restoring the instruction execution context.

In this embodiment, the target instruction is processed after thedisassembling step; in other embodiments, target instructions may beprocessed directly by omitting the assembling and disassembling steps.

In step S4044, for store and read instructions, the target or sourceaddress in the store or read instruction is modified to achieve datadump, which is to save data onto a safety device for data security. Moredetails will be discussed in the following embodiments of the presentdisclosure.

For an I/O instruction, according to a fifth embodiment of the presentdisclosure, there is provided a runtime instruction recombinationmethod, including:

S501, storing a current instruction execution context;

S502, searching an address corresponding table with value A of anaddress register in the stored instruction execution context;

S503, if a corresponding record is found, modifying value A of theaddress register to value A′ of the record, and restoring theinstruction execution context;

S504, if no record is found, a generating method of a recombinedinstruction includes:

S5041, acquiring a machine instruction segment to be scheduled;

S5042, disassembling the machine instruction segment into an assemblyinstruction segment;

S5043, analyzing the assembly instruction segment by using aninstruction set to identify the assembly instruction segment, so as toacquire a target assembly instruction to be processed; the targetassembly instruction being a I/O instruction;

S5044, if the assembly instruction segment includes an I/O instruction,blocking all input instructions in the I/O instruction;

S5045, inserting a second control transfer instruction JP2 before thelast instruction of the assembly instruction segment, the second controltransfer instruction JP2 pointing to an entry address of the instructionrecombination platform, which generates a recombined instruction segmentwith an address of A″;

S5046, assembling the modified assembly instruction segment to get arecombined machine instruction segment;

S5047, creating a record in the address corresponding table with theaddress A″ and address A;

S5048, modifying the value A of the address register in the storedinstruction execution context to the address A″;

S505, restoring the instruction execution context.

In this embodiment, the target instruction is processed after thedisassembling step; in other embodiments, target instructions may beprocessed directly by omitting the assembling and disassembling steps.

In the step S5044, all input instructions in the I/O instruction areblocked, to prevent a local hardware from writing operation; togetherwith the process of store instruction in the last embodiment, all inputinstructions except store instruction can be blocked, which can improvethe data security in computing device.

For a network transmission instruction, according to a sixth embodimentof the present disclosure, there is provided a runtime instructionrecombination method including:

S601, storing a current instruction execution context;

S602, searching an address corresponding table with value A of anaddress register in the stored instruction execution context;

S603, if a corresponding record is found, modifying the value A of theaddress register to value A′ of the record, and restoring theinstruction execution context;

S604, if no record is found, a generating method of a recombinedinstruction includes:

S6041, acquiring a machine instruction segment to be scheduled;

S6042, disassembling the machine instruction segment into an assemblyinstruction segment;

S6043, analyzing the assembly instruction segment by using aninstruction set to identify the assembly instruction segment, so as toacquire a target assembly instruction to be processed; the targetassembly instruction being a network transmission instruction;

S6044, if the assembly instruction segment includes a networktransmission instruction, determining if a destination address of thenetwork transmission instruction which corresponds to a remote computingdevice is a permitted address; and if the destination address is not apermitted address, blocking the network transmission instruction;

S6045, inserting a second control transfer instruction JP2 before thelast instruction of the assembly instruction segment, the second controltransfer instruction JP2 pointing to an entry address of the instructionrecombination platform, which generates a recombined instruction segmentwith an address of A″;

S6046, assembling the modified assembly instruction segment to get arecombined machine instruction segment;

S6047, creating a record in the address corresponding table with theaddress A″ and address A;

S6048, modifying the value A of the address register in the storedinstruction execution context to the address A″;

S605, restoring the instruction execution context.

In this embodiment, the target instruction is processed after thedisassembling step; in other embodiments, target instructions may beprocessed directly by omitting the assembling and disassembling steps.

In step S6044, a network transmission instruction is processed to checkif its destination address which corresponds to a remote computingdevice is a permitted address; if not, the network transmissioninstruction is blocked to realize secure data transmission.

The address corresponding table in the above embodiments are created andmaintained by the instruction recombination platform, which may have afixed-length array structure, a variable-length linked list structure,or other proper data structures for saving data pairs. Optionally, thelength is adjustable and the space of the data structure can bereleased. The operation of releasing the space occupied by the addresscorresponding table may be performed periodically or in a random manner.In some embodiments, the address corresponding table further includes adata field saving the time for creating a record, which is used by thereleasing operation to remove records according to the existence time.In some embodiments, the address corresponding table further includes adata field which is used as a usage counter; in the step of searchingthe address corresponding table, if a record is found, this field isupdated or modified; and it is also used by the releasing operation todelete records according to the usage counter.

Further, in order to perform runtime instruction monitoring since thesystem startup and to achieve a full monitoring of the runtimeinstructions during operation stage of a computing device, according toanother embodiment of the present disclosure, the load instruction whichis used at the system startup is modified, and the instructionrecombination platform provided in the present disclosure is called toperform the runtime instruction recombination method before theexecution of the load instruction; since the jump address of the loadinstruction is a fixed known address, the instruction recombinationplatform may create the address corresponding table with a first recordand create a first recombined instruction segment in advance.

Further, according to the present disclosure, there is also provided acomputer readable medium storing a computer program for causing acomputer to execute instructions according to runtime instructionrecombination methods provided by the above embodiments.

According to another aspect and corresponding to the above runtimeinstruction recombination methods, there is provided a runtimeinstruction recombination device in a seventh embodiment of the presentdisclosure.

As illustrated in FIG. 5, the instruction recombination device 500includes:

an instruction execution context store and restore unit 501, beingadapted to store and restore an instruction execution context;

an instruction acquiring unit 502, being adapted to acquire a machineinstruction segment to be scheduled, after the instruction executioncontext store and restore unit 501 stores the instruction executioncontext;

an instruction recombination unit 503, being adapted to analyze andmodify the machine instruction segment to be scheduled and to generate arecombined instruction segment with address A″; and

an instruction replacing unit 504, being adapted to modify value of theaddress register in the stored instruction execution context to anaddress of the recombined instruction segment.

The instruction execution context store and restore unit 501 is coupledto the instruction acquiring unit 502 and the instruction replacing unit504; the instruction acquiring unit 502, instruction recombination unit503 and instruction replacing unit 504 are coupled in turn, which meansthat the instruction acquiring unit 502 is coupled to the instructionrecombination unit 503 and the instruction recombination unit 503 iscoupled to the instruction replacing unit 504.

The instruction recombination device 500 performs the runtimeinstruction recombination method in the following way:

first, the instruction execution context store and restore unit 501stores the instruction execution context, which is to pushinstruction-execution-related register data onto a stack (e.g. a stackin memory);

then, the instruction acquiring unit 502 reads the address of themachine instruction to be scheduled from a CPU address register, andreads a machine instruction segment according to the address, the lastinstruction of the machine instruction segment being a control transferinstruction. Specifically, the instruction acquiring unit 502 reads anaddress of the machine instruction to be scheduled from a CPU addressregister 511, searches the machine instructions corresponding to theaddress using control transfer instruction as the search target until afirst control transfer instruction (e.g. the control transferinstruction includes JMP instruction and CALL instruction) is found,defines the first control transfer instruction and all machineinstructions before it as a machine instruction segment to be scheduled,and stores the machine instruction segment in the instructionrecombination device 500 or other storage locations which theinstruction recombination device 500 can access;

then, the instruction recombination unit 503 inserts a second controltransfer instruction before the last instruction of the acquired machineinstruction segment, the second control transfer instruction pointing toan entry address of the instruction recombination device, whichgenerates a recombined instruction segment with address A″;

then, the instruction replacing unit 504 modifies the value A of theaddress register in the stored instruction execution context to theaddress A″; and

finally, the instruction execution context store and restore unit 501restores the instruction execution context, which is to popinstruction-execution-related register data from the stack.

Further, according to an eighth embodiment of the present disclosure,there is provided a runtime instruction recombination device, whichutilizes repeatability of instructions in execution to improve therecombination efficiency and save computing resource of the computingdevice.

As shown in FIG. 6, the instruction recombination device 600 includes:

an instruction execution context store and restore unit 601, beingadapted to store and restore instruction execution context;

an instruction acquiring unit 602, being adapted to acquire the machineinstruction segment to be scheduled after the instruction executioncontext store and restore unit 601 stores the instruction executioncontext;

an instruction recombination unit 603, being adapted to analyze andmodify the machine instruction segment to be scheduled, to generate arecombined instruction segment with address A″;

an instruction replacing unit 604, being adapted to modify a value of anaddress register in the stored instruction execution context to theaddress of the recombined instruction segment; and

an instruction searching unit 605, being adapted to search an addresscorresponding table using value A of the address register in the storedinstruction execution context as a searching target; the addresscorresponding table being used to show if the machine instructionsegment corresponding to the address A, which is to be recombined, has astored recombined instruction segment with an address of A′; if acorresponding record is found, the instruction searching unit beingadapted to call the instruction replacing unit to modify the value A ofthe address register to the value A′ of the record; if no record isfound, the instruction searching unit being further adapted to create arecord in an address corresponding table with the address A and addressA″ of a recombined result.

The instruction execution context store and restore unit 601 is coupledto the instruction searching unit 605 and instruction replacing unit604; the instruction searching unit 605 is coupled to the instructionacquiring unit 602, the instruction recombination unit 603 and theinstruction replacing unit 604; and the instruction acquiring unit 602,instruction recombination unit 603 and the instruction replacing unit604 are coupled in turn.

The instruction recombination device 600 performs the runtimeinstruction recombination method in the following way:

first, the instruction execution context store and restore unit 601stores the instruction execution context, which is to pushinstruction-execution-related register data onto a stack;

then, the instruction searching unit 605 searches an addresscorresponding table using the value A of the address register in thestored instruction execution context as the searching target;

where if a record is found in the address corresponding table, theinstruction searching unit 605 calls the instruction replacing unit 604,the instruction replacing unit 604 modifies the value A of the addressregister to the value A′ of the record; and the instruction replacingunit 604 calls the instruction execution context store and restore unit602 to restore the instruction execution context, i.e. to popinstruction-execution-related register data from the stack, andrecombination process is finished; and

if no record is found in the address corresponding table, theinstruction searching unit 602 reads the address of the machineinstruction to be scheduled from the CPU address register, and reads amachine instruction segment according to the address, the lastinstruction of the machine instruction segment being a control transferinstruction. In specific, the instruction acquiring unit 602 reads anaddress of the machine instruction to be scheduled from the CPU addressregister 611, searches the machine instructions corresponding to theaddress using control transfer instruction as the search target until afirst control transfer instruction (e.g. the control transferinstruction includes JMP instruction and CALL instruction) is found,defines the first control transfer instruction and all machineinstructions before it as a machine instruction segment to be scheduled,and stores the machine instruction segment in the instructionrecombination device 600 or other storage locations which theinstruction recombination device 600 can access;

then, the instruction recombination unit 603 inserts a second controltransfer instruction before the last instruction of the acquired machineinstruction segment, the second control transfer instruction pointing toan entry address of the instruction recombination device, whichgenerates a recombined instruction segment with address A″;

then, the instruction recombination unit 603 sends the address A″ toinstruction searching unit 605, and the instruction searching unit 605creates a record in the address corresponding table with address A″ andaddress A, which is for reuse in the future;

then, the instruction replacing unit 604 modifies the value A of theaddress register in the stored instruction execution context to theaddress A″;

finally, the instruction execution context store and restore unit 601restores the instruction execution context, which is to pop theinstruction-execution-related register data from the stack.

In this embodiment, the instruction recombination unit 603 furtherincludes:

an instruction analysis unit 6031, being adapted to use an instructionset to identify the machine instruction segment in order to acquire atarget machine instruction that is to be processed; the instruction setsincluding X86, MIPS and ARM instruction set; and

an instruction modification unit 6032, being adapted to modify or changethe target machine instruction in a preset way.

If the target instruction is a store/read or save/read instruction, theinstruction analysis unit 6031 is used to acquire the store/readinstruction from the machine instruction segment to be scheduled, andthe instruction modification unit 6032 is used to modify the store orread address in the store/read instruction to corresponding addresses ona safety device. The effect is the same as the above correspondingembodiments of methods.

If the target instruction is an I/O instruction, the instructionanalysis unit 6031 is used to acquire the I/O instruction from themachine instruction segment to be scheduled, and the instructionmodification unit 6032 is used to block all input instructions of theI/O instruction. The effect is the same as the above correspondingembodiments of methods.

If the target instruction is a network transmission instruction, theinstruction analysis unit 6031 is used to acquire the networktransmission instruction from the machine instruction segment to bescheduled, and the instruction modification unit 6032 is used to checkif a destination address of the network transmission instruction whichcorresponds to a remote computing device is a permitted address. If thedestination address is not a permitted address, the instructionmodification unit is also used to block the network transmissioninstruction. The effect is the same as the above correspondingembodiments of methods.

According to a ninth embodiment of the present disclosure, as shown inFIG. 7, the instruction recombination unit 703 further includes adisassembling unit 7031 and an assembling unit 7034. The disassemblingunit 7031, an instruction analysis unit 7032, an instructionmodification unit 7033 and the assembling unit 7034 are coupled in turn.Other units in this embodiment are the same as those in the eighthembodiment of the present disclosure.

The disassembling unit 7031 is adapted to disassemble the machineinstruction segment to be scheduled before analyzing and modifying theinstruction segment, which generates an assembly instruction segment tobe scheduled; and is adapted to send the assembly instruction segment tothe instruction analysis unit 7032.

The assembling unit 7034 is adapted to assemble the recombined assemblyinstruction segment after analyzing and modifying the instructionsegment, which generates a recombined machine instruction segment; andis adapted to send the recombined instruction segment in machine code tothe instruction replacing unit.

In this embodiment, the instruction analysis unit 7032 and instructionmodification unit 7033 is to handle the assembly instruction segment tobe scheduled in the same way as described in previous embodiments.

In the above embodiments, the runtime instruction recombination methodand device provided in embodiments of the present disclosure aredescribed in detail; compared with the prior art, there are advantageousincluding:

instructions executed in a computing device are monitored by theinstruction recombination method;

instruction recombination efficiency is improved and computing resourcecan be saved by the address corresponding table;

for store and read instructions, data dump is achieved by modifying thedestination and source address in store and read instructions, whichsave data onto a safety device to guarantee data security;

for I/O instructions, all input instructions in I/O instruction can beblocked, which prevents the local hardware from write operation; and allinput instructions except store instruction can be blocked, which canimprove the data security in a computing device;

for network transmission instructions, by determining if a destinationaddress of the network transmission instruction which corresponds to aremote computing device is a permitted address and by blocking thenetwork transmission instruction if the destination address is not, itachieves data safety transmission.

For target instruction that is store/read instruction, there will bemore embodiments below; and in these embodiment, there are provided adata safety storage and reading method as well as a data safety storageand reading device.

As described in the background, when a computing device such as acomputer or a smart phone is invaded by malicious codes, the maliciouscodes can obtain data from the computing device. After obtaining data,the behavior model of malicious codes includes: (1) storage action: tostore the target data in a certain storage location; (2) transmissionaction: to transmit the stolen data directly to a designated destinationaddress through internet. In addition, the behavior model of divulgingsecrets by the personnel who use the above computing device includes:(1) actively divulging secrets: secret-related personnel directlyacquires confidential information by active copy, malicious tools whichpenetrate safety system, or Trojan horses; (2) passively divulgingsecrets: computing devices or storage medium used by secret-relatedpersonnel are lost or misused such as directly connecting asecret-related device to the Internet which divulges secrets.

To solve the above problems, embodiments of the present disclosure willbe described in detail with reference to accompanying drawingshereinafter. FIG. 8 is a schematic diagram of a hierarchical structureof a computer terminal system in a tenth embodiment of the presentdisclosure. A computer terminal system 200 includes a user interfacelayer 201, an application layer 202, an operating system kernel layer203, a hardware mapping layer 204, a security layer 205, and a hardwarelayer 206; and the computer terminal system 200 is coupled to a storagedevice 100 (i.e. a safety device). The hardware layer 206 includes a CPU2061, a hard disk 2062 (i.e. a local storage device) and a network card2063. In this embodiment, the storage device 100 is a remote disk array,which exchanges data with the computer terminal system 200 by connectingwith the network card 2063 in hardware layer 206. In other embodimentsof the present disclosure, the storage device 100 may also be othertypes of storage equipment.

Referring to the above hierarchical structure and referring to FIG. 9,the data dump process provided by this embodiment includes:

S1000, initialization;

S2000, data write process or data writing process; and

S3000, data read process or data reading process.

In other embodiments, the initialization, data write and data readprocess can be selectively carried out as required.

Further, referring to FIG. 10, the initialization process S1000includes:

S1010, establishing a communication between the computer terminal system200 and the storage device 100 (i.e. safety device); and

S1020, synchronizing a bitmap from the storage device 100 to the currentcomputer terminal system 200, and storing the bitmap in the memory ofthe computer terminal system 200; the bitmap being used to representwhether or not data of local storage address is stored onto the safetydevice.

To distinguish the bitmap of the computer terminal system 200 from thatof the storage device 100, hereinafter, the bitmap of the computerterminal system 200 is, unless otherwise specified, referred to as afirst bitmap or bitmap, and the bitmap in the storage device 100 isreferred to as a second bitmap.

If synchronizing the second bitmap from the storage device 100 to thecurrent computer terminal system 200 fails, it means that the storagedevice 100 and the computer terminal system 200 is connected for thefirst time, or that there was no storage operation in the computerterminal system 200 during the last connection. The initializationprocess S1000 further includes:

S1030, creating a bitmap on the storage device 100 and in the computerterminal system 200 respectively.

Specifically, first, the local storage space of the computer terminalsystem is mapped to the storage device 100, where the mapping relationis one-to-one mapping with sector (or other basic unit of storage) asunit, and a bitmap is created. In other embodiments of the presentdisclosure, other basic unit of storage can be used as unit to establishthe bitmap from the local storage space to the storage device 100.

FIG. 11 is a schematic diagram of the bitmap in this embodiment, FIG. 11includes a storage medium 3000 on a local storage device (i.e. a harddisk 2062), and a storage medium 4000 on the storage device 100 which isconnected to the local storage device through network. For the storagemedium 3000, a storage space 4010 having the same size is established onthe storage medium 4000, which is used as the one-to-one mapping space.At this time, there is only one bitmap 4020 in the storage space 4010.The bitmap 4020 is a bit map, in which one bit represents one sector andthe data (0 or 1) of the bit represents whether or not the correspondingsector of the storage medium 3000 is stored onto the storage space 4010of the storage medium 4000. In this embodiment, sectors which data isstored onto the storage space 4010 of the storage medium 4000 are markedwith 1, and sectors which data is not are marked with 0. After thebitmap 4020 is created, it is synchronized to the computer terminalsystem 200. When an application or the operating system is to save data,e.g. a file, the file system of the operating system allocates a certainamount of storage space on the storage medium 3000 of the local storagedevice, e.g. sector 3040 and sector 3050, assigns the storage space tothe file, and updates the local file allocation table. When the file issaved onto the storage space 4010 of the storage medium 4000 (i.e. thefile is data dumped), bit data of the bitmap corresponding to the sector3040 and sector 3050 are changed to 1, while sector 4040 and sector 4050are allocated on corresponding positions on the storage medium 4000 tosave the file.

After the initialization process is finished in this embodiment, thecomputer terminal system 200 and the storage device 100 store twobitmaps with the same data.

Further, the data write process S2000 includes:

S2010, the application layer 202 makes an operation request of writingfile through the file system of the operating system kernel layer 203,or the operating system kernel layer 203 makes an operation request ofwriting file directly; or the application layer 202 makes an operationrequest of writing data to the hardware mapping layer 204 directly, orthe operating system kernel layer 203 makes an operation request ofwriting data to the hardware mapping layer 204 directly;

S2020, the operating system kernel layer 203 translates the operationrequest of writing file to hardware port instructions (i.e. hardwareinstruction), and sends the hardware port instructions to the hardwaremapping layer 204, the hardware port instructions containing the storageposition (i.e. sector) to be written on; if operation request of writingdata is made directly to the hardware mapping layer 204, the request isalready a hardware port instruction; and

S2030, the security layer 205 modifies the writing position (i.e.sector) in the port instruction to the storage address on the storagedevice 100, updates the first bitmap by changing the bit datacorresponding to the sector to 1 which represents this sector is datadumped; and the security layer 205 then sends the modified portinstruction to the hardware layer 206.

After the above processes, the writing process S2000 can furtherinclude:

S2040, the first bitmap is synchronized to the storage device 100 andsaved as a second bitmap, which guarantees that the first bitmap on thecomputer terminal system 200 and the second bitmap on the storage deviceare the same. In other embodiments of the present disclosure, thissynchronization operation can be carried out at last, e.g. before thecomputer terminal system 200 is power off.

After the writing process is carried out, the computer terminal system200 doesn't store the writing data, since the writing data has beendumped or stored on the storage device 100.

Further, the data read process S3000 includes:

S3010, the second bitmap on the storage device 100 is synchronized tothe computer terminal system 200 and saved as the first bitmap;

S3020, the application layer 202 makes an operation request of readingfile through the file system of the operating system kernel layer 203,or the operating system kernel layer 203 makes an operation request ofreading file directly; or the application layer 202 makes an operationrequest of reading data to the hardware mapping layer 204 directly, orthe operating system kernel layer 203 makes an operation request ofreading data to the hardware mapping layer 204 directly; and

S3030, the security layer 205 receives a data read instruction from thehardware mapping layer 204, and acquires a read address (or sourceaddress) of the data read instruction; if this address is not an addressof the storage device 100, the security layer searches the first bitmap,and if the bit data in the first bitmap corresponding to the readaddress represents that the data of the read address is dumped, thesecurity layer 205 modifies the read address of the port instruction tothe corresponding read address of the storage device 100; and thesecurity layer 205 sends the modified port instruction to the hardwarelayer 206.

In step S3010, synchronizing the second bitmap from the storage device100 to the computer terminal system 200 is to keep the consistencybetween the local data and the data on the safety device after thereboot of the computer terminal system 200.

The above read process does not affect the current operation mode ofusers, and realizes data read operation of the dumped data on the safetydevice (i.e. the storage device 100).

Further, based on the above data write process and referring to FIG. 12,a data safety storage method provided in the embodiment includes:

S4010, receiving a hardware instruction;

S4020, analyzing the hardware instruction;

S4030, determining if the hardware instruction is a store instruction;

S4040, if the hardware instruction is a store instruction, modifying adestination address in the store instruction to the correspondingstorage address on the storage device 100 (i.e. safety device); and

S4050, sending the modified store instruction to a hardware layer.

Specifically, in this embodiment, the operating system running on thecomputer terminal system is Windows operating system, and in Windows,the hardware mapping layer is hardware abstract layer (HAL). In otherembodiments, the operating system running on the computer terminalsystem can be Linux, UNIX or embedded operating system, and the hardwaremapping layer is a layer corresponding to the HAL of Windows.

In step S4010, the hardware instruction is the hardware instruction fromhardware mapping layer. Receiving hardware instructions from thehardware mapping layer can fully screen the hardware instructions (i.e.port instructions) sent to the processor such as CPU, which furtherimproves the data security. In other embodiments of the presentdisclosure, the hardware instruction can also come from the operatingsystem kernel layer or units corresponding to other computer layers.

In addition, together with the runtime instruction recombination methodas discussed above, the process of receiving a hardware instruction mayinclude: acquiring a hardware instruction using the runtime instructionrecombination method.

In step S4020, there are various instruction analysis mechanisms withinthe security layer 205 to handle different types of CPU instruction,such as X86 instruction set, ARM instruction set, MIPS instruction set,etc.

In step S4040, after modifying a destination address in the storeinstruction to the corresponding storage address on the storage device100, the method can further include: updating the first bitmap bysetting the ‘bit’ of the first bitmap which corresponds to thedestination address (sector) to 1.

Further, in step S4040, the method can further include: synchronizingthe updated bitmap to the safety device saving as a second bitmap.

In step S4050, the security layer 205 forwards modified or unmodifiedhardware instructions to the hardware layer 206. In this embodiment, thedata-dump operation (which is to save local data onto the safety device)of the security layer 205 is completely transparent to upper layers orusers, which does not affect the work flow of current computers orapplications.

The methods provided in this embodiment cannot only be used in acomputer terminal system, but also be used in any computing devices orintelligent terminals that include an application layer, an operatingsystem kernel layer and a hardware layer, which achieves instructionlevel data dump (i.e. data dump based on hardware store instruction)before the hardware layer carries out instructions.

According to the above data read process, referring to FIG. 13, a datasafety reading method provided in the embodiment includes:

S5010, receiving a hardware instruction;

S5020, analyzing the hardware instruction;

S5030, determining if the hardware instruction is a read instruction;

S5040, if the hardware instruction is a read instruction, acquiring asource address of the read instruction, and determining if the sourceaddress is an address of the storage device 100;

S5050, if the source address is not an address of the storage device100, searching the first bitmap, and modifying the read address of theread instruction according to the data of the bitmap; and

S5060, sending the modified hardware instruction to a hardware layer.

Before the step S5010, the method can further include: S5000,synchronizing a second bitmap on the storage device 100 to the computerterminal system 200 saving as a first bitmap. In the step S5010 of thisembodiment, the hardware instruction comes from a hardware mappinglayer.

In addition, together with the above runtime instruction recombinationmethod, receiving a hardware instruction may include: acquiring ahardware instruction using the runtime instruction recombination method.

In step S5030, if the hardware instruction is not a read instruction,the security layer 205 directly sends the hardware instruction to thehardware layer for execution.

In step S5040, if the source address is already an address of thestorage device 100, the security layer 205 does not have to search thefirst bitmap but sends the hardware instruction to the hardware layerfor execution.

Further, to save network resource, in some embodiments of the presentdisclosure, the storage device 100 can be shared among a plurality ofterminal systems.

Further, based on the above data safety storage and data safety readingmethod, according to the eleventh embodiment of the present disclosure,there is provided a data safety transmission method. As shown in FIG.14, the data safety transmission method includes:

S7010, receiving a hardware instruction form a hardware mapping layer;

S7020, analyzing the hardware instruction;

S7030, determining if the hardware instruction is a network transmissioninstruction;

S7040, if the hardware instruction is a network transmissioninstruction, reading a destination address;

S7050, determining if the destination address is a permitted address;

S7060, if the destination address is a permitted address, sending thehardware instruction to a hardware layer; and if the destination addressis not a permitted address, blocking the hardware instruction and themethod is finished;

S7070, sending, by the hardware layer, the network transmissioninstruction and data to a terminal system on the destination address;and

S7080, receiving by the terminal system on the destination address thedata, and storing by the terminal system on the destination address thedata with the data safety storage method.

In step S7060, if the destination address is not a permitted address,which means that the terminal system on the destination address does notadopt the data safety storage and data safety reading method provided inthe present disclosure, it is not allowed to be a destination addressfor network transmission operation.

In step S7050, determining if the destination address is a permittedaddress is carried out in the following steps. As shown in FIG. 15, asecurity server 820 is connected with terminal systems 800 and 810through internet; when the data safety transmission method provided inembodiments of the present disclosure is deployed in the terminal system800 and 810, the terminal system 800 and 810 carries out a registrationoperation to the security server 820 automatically; a permitted addresstable is maintained in the security server 820, which records allregistered terminal systems. When the permitted address table isupdated, the security server 820 automatically sends the new permittedaddress table to each terminal. The architecture of the terminal system800 includes an application layer 801, an operating system kernel layer802, a security layer 803 and a hardware layer 804, in which thesecurity layer 803 is responsible for maintaining the permitted addresstable. The security layer 803 determines if the destination address is apermitted address by determining if the destination address is in thepermitted address table. That is to say in step S7050, if a destinationaddress is listed in the permitted address table, the destinationaddress is a permitted address.

By the above data safety transmission method, even if Trojan horses ormalicious tools acquire confidential information, they cannot transmitthe stolen information.

Although methods provided in the present disclosure are described withina computer terminal system, any electronic equipment that can providefile or data editing, saving or transmitting operation, such ashandhelds and intelligent terminals, can be the terminal system thatapplies the data safety storage and transmission method provided in thepresent disclosure.

In addition, one of ordinary skill in the art can appreciate that theabove data safety storage method, data safety reading method and datasafety transmission method can be implemented in software or hardware,if in software, the above method steps can be represented in computercode that is stored in computer readable medium, which can also become asoftware product.

Corresponding to the above data safety storage method, according to atwelfth embodiment of the present disclosure, there is provided a datasafety storage device. Referring to FIG. 16, a data safety storagedevice 7100 includes: a receiving unit 7110, an instruction analysisunit 7120, an instruction modification unit 7130, and a transmittingunit 7140. The receiving unit 7110 is coupled with the instructionanalysis unit 7120, the instruction analysis unit 7120 is also coupledwith the instruction modification unit 7130 and the transmitting unit7140, and the transmitting unit 7140 is also coupled with theinstruction modification unit 7130 and the hardware layer 7200.

The receiving unit 7110 is adapted to receive a hardware instruction,and the hardware instruction comes from the hardware mapping layer inthis embodiment; the instruction analysis unit 7120 is adapted toanalyze the hardware instruction and to determine if the hardwareinstruction is a store instruction; if the hardware instruction is astore instruction, the instruction modification unit 7130 modifies thedestination address of the store instruction to a corresponding storageaddress on a safety device, and sends the modified store instruction tothe transmitting unit 7140; if the hardware instruction is not a storeinstruction, the instruction analysis unit 7120 sends the hardwareinstruction directly to the transmitting unit 7140; the transmittingunit 7140 is adapted to send the received instruction to the hardwarelayer 7200.

Further, the data safety storage device can also include an updatingunit 7150 and a synchronization unit 7160, in which the updating unit7150 is coupled with the instruction modification unit 7130 and thesynchronization unit 7160 is coupled with the updating unit 7150.

The updating unit 7150 is adapted to update the bit that corresponds tothe destination address in the bitmap after the instruction modificationunit 7130 modifies the store instruction. In this embodiment, the ‘bit’data which corresponds to the sector at the destination address of thestore instruction is set to ‘1’ to represent that the sector is datadumped.

The synchronization unit 7160 is adapted to establish the communicationbetween the computer terminal system and the safety device, and toperform synchronization operation of the bitmap between the computerterminal system and the safety device. Specifically, when the computerterminal system starts up, the synchronization unit 7160 establishes thecommunication between the computer terminal system and the safetydevice, and synchronizes a second bitmap of the safety device to thecomputer terminal system saving as a first bitmap.

If it fails to synchronize the second bitmap on the safety device to thecomputer terminal system, it means that this is the first communicationbetween the computer terminal system and the safety device, then thesynchronization unit 7160 maps the local storage space of the computerterminal system to the safety device and creates a first bitmap and asecond bitmap. In this embodiment, the second bitmap on the safetydevice is built firstly and is then synchronized to the computerterminal system saving as the first bitmap.

When the updating unit 7150 updates the bit that corresponds to thedestination address in the first bitmap, the synchronization unit 7160sends the updated first bitmap to the safety device, which is then savedas a second bitmap.

In this embodiment, the safety device is a remote storage device, andmay be shared among multiple computer terminal systems. The hardwareinstruction is a hardware port I/O instruction.

Further, corresponding to the data safety reading method as discussedabove, according to a thirteenth embodiment of the present disclosure,there is provided a data safety reading device. Referring to FIG. 17, adata safety reading device 8100 includes: a receiving unit 8110, aninstruction analysis unit 8120, an instruction modification unit 8130and a transmitting unit 8140. The receiving unit 8110 is coupled withthe instruction analysis unit 8120, the instruction analysis unit 8120is also coupled with the instruction modification unit 8130 and thetransmitting unit 8140 respectively, and the instruction modificationunit 8130 is also coupled with the transmitting unit 8140. Thetransmitting unit 8140 is coupled with the hardware layer 8200.

The receiving unit 8110 is adapted to receive a hardware instruction,and the hardware instruction comes from the hardware mapping layer inthis embodiment. The instruction analysis unit 8120 is adapted toanalyze the hardware instruction and to determine if the hardwareinstruction is a read instruction, and if the hardware instruction is aread instruction, the instruction analysis unit 8120 is also adapted toacquire the source address of the read instruction and determine if thesource address is an address on the safety device. If the hardwareinstruction is not a read instruction or the source address is anaddress on the safety device, the instruction analysis unit 8120 sendsthe hardware instruction to the transmitting unit 8140. If the sourceaddress is not an address on the safety device, the instructionmodification unit 8130 looks up the bitmap, and modifies the readaddress of the read instruction according to the data of the bitmap.Similar to the above bitmap, the bitmap in this embodiment is used torepresent whether or not data of local storage address is saved or datadumped onto the safety device. Specifically, the instructionmodification unit 8130 searches for the bit that corresponds to thesector at the source address in the first bitmap. If the ‘bit’ datashows 1, it means that data dump has been performed; if the ‘bit’ datashows 0, it means that data dump has not been performed. If data dumphas been performed, the instruction modification unit 8130 modifies thesource address (or read address) to a corresponding data dump address,and sends the modified hardware instruction to the transmitting unit8140.

Further, the data safety reading device may also include asynchronization unit 8150. The synchronization unit 8150 is coupled withthe instruction modification unit 8130. And the synchronization unit8150 is adapted to establish a communication between the computerterminal system and the safety device, and to synchronize bitmapsbetween the computer terminal system and the safety device.Specifically, when the computer terminal system starts up, thesynchronization unit 8150 establishes the communication between thecomputer terminal system and the safety device, and synchronizes asecond bitmap of the safety device to the computer terminal system,which is saved as a first bitmap and to be used by the instructionmodification unit 8130.

In this embodiment, the safety device is a remote storage device whichmay be shared among multiple computer terminal systems. In otherembodiments of the present disclosure, the safety device may be a localstorage device.

One of ordinary skill in the art would appreciate that the above methodused in the security layer may also be used in various layers from theoperating system kernel layer to the hardware layer. Variousmodifications can be made to choose different layer to implement theabove method or device provided by the present disclosure withoutdeparting from the scope of spirit of the disclosure.

Data safety storage method and device provided in the present disclosureare described in detail in the above embodiments; compared with theconventional art, the method and device have the followingadvantages: 1. the data safety storage method achieves an instructionlevel data dump which is a full data dump, and achieves data safetystorage during the full operation time of a computer terminal systembased on the full data dump; on the one hand, even if Trojan horses ormalicious tools have acquired confidential information, they cannot savethe stolen data, which guarantees that data are in security zone undercontrol, on the other hand, no confidential information or data is savedlocally, which prevents secret-related personnel from divulging secretsactively or passively; 2. By receiving hardware instructions from thehardware mapping layer, it can screen instructions 100%, which furtherimproves data security.

Data safety reading method and device provided in the present disclosureare described in detail in the above embodiments; compared with theconventional art, the method and device has the following advantages: 1.together with the data safety storage method, the data safety readingmethod guarantees that all data are in security zone under control, andthat dumped data can be accessed or read; and since no confidentialinformation or data is saved locally, it prevents secret-relatedpersonnel from divulging secrets actively or passively; 2. when thesafety device is a remote storage device, it may be shared by multipleterminals, which improves space use efficiency of the safety device.

In other embodiments of the present disclosure, the above method used inthe security layer may also be implemented in various layers from thebottom layer of the operating system to the upper layer of the hardwarelayer. One of ordinary skill in the art would appreciate that variousmodifications can be made to choose a different layer to implement theabove methods or devices provided in the embodiments of the presentdisclosure without departing from the scope of spirit of the disclosure.

The above are only specific embodiments of the disclosure which are usedto make those skilled in the art better understand the spirit of thedisclosure, however, the scope of protection of the disclosure shouldnot be limited to the specific descriptions of the specific embodiments,various modifications can be made to the specific embodiments of thedisclosure by those skilled in the art without departing from the scopeof spirit of the disclosure.

What is claimed is:
 1. A method for controlling running of instructions,comprising: storing an instruction execution context; acquiring amachine instruction segment to be scheduled to an instructionrecombination platform, where the machine instruction segment to bescheduled contains a first control transfer instruction at an end of themachine instruction segment to be scheduled, and a value of an addressregister in the instruction execution context represents an originaladdress of the machine instruction segment to be scheduled; inserting asecond control transfer instruction before the first control transferinstruction to form a current recombined instruction segment; modifyingthe value of the address register in the instruction execution contextto a current address of the current recombined instruction segment;restoring the instruction execution context; and executing the currentrecombined instruction segment according to the current address of thecurrent recombined instruction segment, where when the second controltransfer instruction is executed, a next machine instruction segment tobe scheduled starts to be acquired to the instruction recombinationplatform.
 2. The method of claim 1, wherein acquiring a machineinstruction segment to be scheduled comprises: reading the originaladdress of the machine instruction segment to be scheduled from theaddress register; and reading the machine instruction segment to bescheduled according to the original address of the machine instructionsegment to be scheduled and the first control transfer instruction. 3.The method of claim 2, wherein reading the machine instruction segmentto be scheduled according to the original address of the machineinstruction segment to be scheduled and the first control transferinstruction comprises: searching machine instructions corresponding tothe original address of the machine instruction segment to be scheduleduntil the first control transfer instruction is found, the first controltransfer instruction comprising JMP instruction and CALL instruction. 4.The method of claim 1, wherein after storing the instruction executioncontext and before acquiring the machine instruction segment to bescheduled, the method further comprises: searching an addresscorresponding table according to the original address of the machineinstruction segment to be scheduled, where the address correspondingtable is used for storing corresponding relationships between originaladdresses of machine instruction segments to be scheduled and currentaddresses of corresponding recombined instruction segments; and if theoriginal address of the machine instruction segment to be scheduled isfound in the address corresponding table, modifying the value of theaddress register to a current address of corresponding recombinedinstruction segment and restoring the instruction execution context. 5.The method of claim 4, further comprising: if the original address ofthe machine instruction segment to be scheduled is not found in theaddress corresponding table, creating a record in the addresscorresponding table with the original address of the machine instructionsegment to be scheduled and the current address of the currentrecombined instruction segment.
 6. The method of claim 1, wherein beforeinserting the second control transfer instruction, the method furthercomprises: analyzing the machine instruction segment to be scheduled byusing an instruction set to identify the machine instruction segment tobe scheduled, in order to acquire a target machine instruction to beprocessed; and modifying the target machine instruction in a preset way.7. The method of claim 6, wherein the target machine instruction is astore or read instruction; and modifying the target machine instructionin a preset way comprises: modifying a store or read address of thestore or read instruction to a corresponding address on a safety device.8. The method of claim 6, wherein the target machine instruction is anI/O instruction; and modifying the target machine instruction in apreset way comprises: blocking input instructions in the I/Oinstruction.
 9. The method of claim 6, wherein the target machineinstruction is a network transmission instruction; and modifying thetarget machine instruction in a preset way comprises: determining if adestination address in the network transmission instruction whichcorresponds to a remote computing device is a permitted address; and ifthe destination address is not a permitted address, blocking the networktransmission instruction.
 10. A non-transitory computer readable medium,having a computer executable program stored thereon which, when executedby a computer, causes the computer to perform the method of claim
 1. 11.A device for controlling running of instructions, comprising: aninstruction execution context store and restore unit, being adapted tostoring and restoring an instruction execution context; an instructionacquiring unit, being adapted to acquiring a machine instruction segmentto be scheduled to an instruction recombination platform after theinstruction execution context store and restore unit stores theinstruction execution context, where the machine instruction segment tobe scheduled contains a first control transfer instruction at an end ofthe machine instruction segment to be scheduled, and a value of anaddress register in the instruction execution context represents anoriginal address of the machine instruction segment to be scheduled; aninstruction recombination unit, being adapted to inserting a secondcontrol transfer instruction before the first control transferinstruction to form a current recombined instruction segment; aninstruction replacing unit, being adapted to modifying the value of theaddress register in the instruction execution context to a currentaddress of the current recombined instruction segment; and aninstruction execution unit, being adapted to executing the currentrecombined instruction segment according to the current address of thecurrent recombined instruction segment, where when the instructionexecution unit executes the second control transfer instruction, theinstruction acquiring unit starts to acquire a next machine instructionsegment to be scheduled.
 12. The device of claim 11, wherein theinstruction acquiring unit is adapted to reading the original address ofthe machine instruction to be scheduled from the address register, andadapted to reading the machine instruction segment to be scheduledaccording to the original address of the machine instruction to bescheduled and the first control transfer instruction.
 13. The device ofclaim 12, wherein the instruction acquiring unit is adapted to searchingmachine instructions corresponding to the original address of themachine instruction segment to be scheduled until the first controltransfer instruction is found, the first control transfer instructioncomprising JMP instruction and CALL instruction.
 14. The device of claim11, further comprising: an instruction searching unit, being adapted tosearch an address corresponding table according to the original addressof the machine instruction segment to be scheduled, where the addresscorresponding table is used for storing corresponding relationshipsbetween original addresses of machine instruction segments to bescheduled and current addresses of corresponding recombined instructionsegments; where if the original address of the machine instructionsegment to be scheduled is found in the address corresponding table, theinstruction searching unit is adapted to calling the instructionreplacing unit to modify the value of the address register to a currentaddress of corresponding recombined instruction segment; and if theoriginal address of the machine instruction segment to be scheduled isnot found in the address corresponding table, the instruction searchingunit is adapted to creating a record in the address corresponding tablewith the original address of the machine instruction segment to bescheduled and the current address of the current recombined instructionsegment.
 15. The device of claim 11, wherein the instructionrecombination unit comprises: an instruction analysis unit, beingadapted to identifying the machine instruction segment to be scheduledby using an instruction set to acquire a target machine instruction tobe processed; and an instruction modification unit, being adapted tomodifying the target machine instruction in a preset way.
 16. The deviceof claim 15, wherein if the target machine instruction is a store orread instruction, the instruction modification unit is adapted tomodifying a store or read address of the store or read instruction to acorresponding address on a safety device.
 17. The device of claim 15,wherein if the target machine instruction is an I/O instruction, theinstruction modification unit is adapted to blocking input instructionsin the I/O instruction.
 18. The device of claim 15, wherein if thetarget machine instruction is a network transmission instruction, theinstruction modification unit is adapted to determining if a destinationaddress in the network transmission instruction which corresponds to aremote computing device is a permitted address; and if the destinationaddress is not a permitted address, the instruction modification unit isadapted to blocking the network transmission instruction.